1. Field of the Invention
The present invention relates to an offset cancel output circuit of a source driver for driving a liquid crystal display.
2. Description of the Related Art
Source drivers for driving a liquid crystal display panel function to cancel an offset component in the drive voltage delivered from an output circuit that includes an operational amplifier (see Japanese Patent Kokai No. H11-044872 (Patent Literature 1) and Japanese Patent Kokai No. 2001-67047 (Patent Literature 2)). FIG. 1 shows the configuration of the conventional offset cancel output circuit that is disclosed in Patent Literature 2. This offset cancel circuit is a capacitor-coupled operational amplifier circuit, which includes an output amplifier 1, an input capacitor Cin, an output capacitor Cout, switching elements SW1 to SW6, and a resistor R1. Furthermore, the offset cancel output circuit is supplied with a reference voltage VOP and a voltage VDAC, as an input voltage. The voltage VDAC is a voltage (gray scale voltage) which is obtained by a D/A (digital to analog) converter (not shown) of the source driver converting digital data to an analog voltage, where the digital data is indicative of a gray scale of each pixel supplied to the source driver. The application terminal supplied with the reference voltage VOP is connected to the non-inverted input port of the output amplifier 1 which includes an operational amplifier. The inverted input port of the output amplifier 1 is connected to one end of each of the input capacitor Cin and the output capacitor Cout. The switching element SW1 is connected between the application terminal supplied with the voltage VDAC and the other end of the input capacitor Cin. The switching element SW2 is connected between the application terminal supplied with the reference voltage VOP and the other end of the input capacitor Cin. The switching element SW3 is connected between the non-inverted input port and the inverted input port of the output amplifier 1. The switching element SW4 is connected between the inverted input port and the output port OUT of the output amplifier 1. The switching element SW5 is connected between the other end of the output capacitor Cout and the output port OUT of the output amplifier 1. The switching element SW6 is connected between the other end of the output capacitor Cout and the application terminal supplied with the reference voltage VOP. The resistor R1 is connected at one end thereof to the output port OUT of the output amplifier 1, so that the output voltage of the output amplifier 1 is to be delivered as a drive voltage from a terminal PAD via the resistor R1.
Such a conventional offset cancel output circuit performs a reset operation and a normal output operation. The reset operation is performed in response to an external reset signal in synchronization with the vertical synchronization signal of a video signal. The voltage VDAC is produced in synchronization with the horizontal synchronization signal during the normal output operation.
First, as shown in FIG. 2, during the reset operation, the switching elements SW1 and SW5 are turned OFF, and the switching elements SW 2, SW3, SW 4, and SW6 are turned ON. Thus, the reset operation is carried out by making the voltages at all the connection points (nodes), shown as black circles in FIG. 2, equal to the reference voltage VOP. That is, the reference voltage VOP is applied to the other end of the input capacitor Cin via the switching element SW2, and at the same time, to the other end of the output capacitor Cout via the switching element SW6. Furthermore, the inverted input port and the non-inverted input port of the output amplifier 1 are short-circuited by the switching element SW3, thereby causing an offset voltage ΔV to be produced at the output port of the output amplifier 1. The offset voltage ΔV is supplied to a connection point FB via the switching element SW4. This causes the offset voltage ΔV to be accumulated in each of the input capacitor Cin and the output capacitor Cout, allowing the output circuit to operate with stability under this condition.
Then, as shown in FIG. 3, a transition from the reset operation to the normal output operation causes the switching elements SW1 and SW5 to be turned ON and the switching elements SW 2, SW3, SW 4, and SW6 to be turned OFF. The connection point FB of the inverted input port is floated, and the output amplifier 1 operates so that the connection point FB is held at the reference voltage VOP. That is, this causes electric charges to flow into the input capacitor Cin according to the voltage difference between the reference voltage VOP and the voltage VDAC, also causing charges to flow into the output capacitor Cout according to the voltage difference between the output voltage of the output amplifier 1 and the reference voltage VOP. As such, the output amplifier 1 produces an output voltage with the offset voltage ΔV cancelled. Furthermore, a voltage associated with the voltage VDAC is applied to the inverted input port via the input capacitor Cin, thus allowing a voltage to be delivered according to the voltage difference between the reference voltage VOP and the inverted input port. During the normal output operation, the output voltage of the output amplifier 1 is delivered as a drive voltage during a write period according to the write signal for every one horizontal period to the pixels of the liquid crystal display panel.